1. Field of the Invention
Embodiments of the present invention generally relate to the fabrication of photovoltaic cells.
2. Description of the Related Art
Solar cells are photovoltaic devices that convert sunlight directly into electrical power. The most common solar cell material is silicon, which is in the form of single or polycrystalline wafers. Because the amortized cost of forming a silicon-based solar cells to generate electricity is higher than the cost of generating electricity using traditional methods, there has been an effort to reduce the cost to form solar cells.
FIGS. 1A and 1B schematically depicts a standard silicon solar cell 100 fabricated on a wafer 110. The wafer 110 includes a p-type base region 101, an n-type emitter region 102, and a p-n junction region 103 disposed therebetween. An n-type region, or n-type semiconductor, is formed by doping the semiconductor with certain types of elements (e.g., phosphorus (P), arsenic (As), or antimony (Sb)) in order to increase the number of negative charge carriers, i.e., electrons. Similarly, a p-type region, or p-type semiconductor, is formed by the addition of trivalent atoms to the crystal lattice, resulting in a missing electron from one of the four covalent bonds normal for the silicon lattice. Thus, the dopant atom can accept an electron from a neighboring atom's covalent bond to complete the fourth bond. The dopant atom accepts an electron, causing the loss of half of one bond from the neighboring atom and resulting in the formation of a “hole”.
When light falls on the solar cell, energy from the incident photons generates electron-hole pairs on both sides of the p-n junction region 103. Electrons diffuse across the p-n junction to a lower energy level and holes diffuse in the opposite direction, creating a negative charge on the emitter and a corresponding positive charge builds up in the base. When an electrical circuit is made between the emitter and the base and the p-n junction is exposed to certain wavelengths of light, a current will flow. The electrical current generated by the semiconductor when illuminated flows through contacts disposed on the frontside 120, i.e. the light-receiving side, and the backside 121 of the solar cell 100. The top contact structure, as shown in FIG. 1A, is generally configured as widely-spaced thin metal lines, or fingers 104, that supply current to a larger bus bar 105. The back contact 106 is generally not constrained to be formed in multiple thin metal lines, since it does not prevent incident light from striking solar cell 100. Solar cell 100 is generally covered with a thin layer of dielectric material, such as Si3N4, to act as an anti-reflection coating 111, or ARC, to minimize light reflection from the top surface of solar cell 100.
In the interest of simplified assembly and higher efficiency of solar cells, a solar cell has been developed, wherein a plurality of holes is formed through the solar cell substrate and serves as vias for interconnection of the top contact structure to a backside conductor by using pins. This solar cell design is referred to as a pin-up module, or PUM. One advantage of the PUM concept is the elimination of the busbars, such as bus bar 105 illustrated in FIG. 1A, from covering the light-receiving side of the substrate, thereby increasing efficiency of the cell. Another is that resistive losses are reduced because current produced by the solar cell is collected at holes equally spaced over the substrate rather than requiring some of the connections to extend across the surface of the solar cell. Further, resistive losses experienced by a PUM connected device will not increase as the solar cell surface area increases and, hence, larger solar cells may be manufactured without a loss in efficiency.
FIG. 1C is a partial schematic cross section of one example of a PUM cell 130 showing a contact 134. Similar to a standard solar cell, such as solar cell 100, PUM cell 130 includes a single crystal silicon wafer 110 with a p-type base region 101, an n-type emitter region 102, and a p-n junction region 103 disposed therebetween. PUM cell 130 also includes a plurality of through-holes 131, which are formed between the light-receiving surface 132 and the backside 133 of PUM cell 130. The through-holes 131 allow the formation of contact 134 between the light-receiving surface 132 and the backside 133. Disposed in each through-hole 131 is a contact 134, which includes a top contact structure 135 disposed on light-receiving surface 132, a backside contact 136 disposed on backside 133, and an interconnect 137, which fills through-hole 131 and electrically couples top contact structure 135 and backside contact 136. An anti-reflective coating 107 may also be formed on light receiving surface 132 to minimize reflection of light energy therefrom. A backside contact 139 completes the electrical circuit required for PUM cell 130 to produce a current by forming an ohmic contact with p-type base region 101 of the silicon wafer 110.
The fingers 104 (FIG. 1B) or contact 134 (FIG. 1C) are in contact with the substrate are adapted to form an ohmic connection with doped region (e.g., n-type emitter region 102). An ohmic contact is a region on a semiconductor device that has been prepared so that the current-voltage (I-V) curve of the device is linear and symmetric, i.e., there is no high resistance interface between the doped silicon region of the semiconductor device and the metal contact. Low-resistance, stable contacts are critical for the performance of the solar cell and reliability of the circuits formed in the solar cell fabrication process. Hence, after the fingers 104, or contacts 134, have been formed on the light-receiving surface and on the backside, an annealing process of suitable temperature and duration is typically performed in order to produce the necessary low resistance metal silicide at the contact/semiconductor interface. A backside contact completes the electrical circuit required for solar cell to produce a current by forming an ohmic contact with p-type base region of the substrate.
Wider the current carrying metal lines (e.g., fingers 104, contact 134) are on the light-receiving surface of the solar cell the lower the resistance losses, but the higher the shadowing losses due to the reduced effective surface area of the light-receiving surface. Therefore, maximizing solar cell efficiency requires balancing these opposing design constraints. FIG. 1D illustrates a plan view of one example of a top contact structure 135 for a PUM cell, wherein the finger width and geometry have been optimized to maximize cell efficiency for the cell. In this configuration, a top contact structure 135 for a PUM cell is configured as a grid electrode 138, which consists of a plurality of various width finger segments 135A. The width of a particular finger segment 135A is selected as a function of the current to be carried by that finger segment 135A. In addition, finger segments 135A are configured to branch as necessary to maintain finger spacing as a function of finger width. This minimizes resistance losses as well as shadowing by finger segments 135A.
Traditionally, the current carrying metal lines, or conductors, are fabricated using a screen printing process in which a silver-containing paste is deposited in a desired pattern on a substrate surface and then annealed. However, there are several issues with this manufacturing method. First, the thin fingers of the conductors, when formed by the screen printing process, may be discontinuous since the fingers formed using a metal paste do not always agglomerate into a continuous interconnecting line during the annealing process. Second, porosity present in the fingers formed during the agglomeration process results in greater resistive losses. Third, electrical shunts may be formed by diffusion of the metal (e.g., silver) from the contact into the p-type base region or on the surface of the substrate backside. Shunts on the substrate backside are caused by poor definition of backside contacts such as waviness, and/or metal residue. Fourth, due to the relatively thin substrate thicknesses commonly used in solar cell applications, such as 200 micrometers and less, the act of screen printing the metal paste on the substrate surface can cause physical damage to the substrate. Lastly, silver-based paste is a relatively expensive material for forming conductive components of a solar cell.
One issue with the current method of forming metal interconnects using a screen printing process that utilizes a metal particle containing paste is that the process of forming the patterned features requires high temperature post-processing steps to densify the formed features and form a good electrical contact with the substrate surface. Due to the need to perform a high temperature sintering process the formed interconnect lines will have a high extrinsic stress created by the difference in thermal expansion of the substrate material and the metal lines. A high extrinsic stress, or even intrinsic stress, formed in the metal interconnect lines is an issue, since it can cause breakage of the formed metallized features, warping of the thin solar cell substrate, and/or delamination of the metallized features from the surface of the solar cell substrate. The high temperature post processing step can also cause the material in the solar cell device to diffuse into unwanted regions of the device, thus causing device problems, such as an electrical short. High temperature processes also limit the types of materials that can be used to form a solar cell due to the breakdown of certain materials at the high sintering temperatures. Also, screen printing processes also tend to be non-uniform, unreliable and often unrepeatable. Therefore, there is a need to form a low stress interconnect line that forms a strong bond to the surface of the substrate.
Another approach to forming very thin, robust current carrying metal lines on the surface of a solar cell substrate involves cutting grooves in the surface of the substrate with a laser. The grooves are subsequently filled by an electroless plating method. However the laser-cut grooves are a source of macro- and micro-defects. The laser-cut edge is not well defined, causing waviness on the finger edges, and the heat of the laser introduces defects into the silicon.
The effectiveness of a solar cell substrate fabrication process is often measured by two related and important factors, which are device yield and the cost of ownership (CoO). These factors are important since they directly affect the cost to produce an solar cell device and thus a device manufacturer's competitiveness in the market place. The CoO, while affected by a number of factors, is greatly affected by the system and chamber throughput or simply the number of substrates per hour processed using a desired processing sequence. A process sequence is generally defined as the sequence of device fabrication steps, or process recipe steps, completed in one or more processing chambers that are used to form a solar cell. A process sequence may generally contain various substrate (or wafer) fabrication processing steps. If the substrate throughput is not limited by the time to transfer the solar cell substrates then the longest process recipe step will generally limit the throughput of the processing sequence, increase the CoO and possibly make a desirable processing sequence impractical.
Therefore, there is a need for a system, a method and an apparatus that can process a substrate so that it can meet the required device performance goals and increase the system throughput and thus reduce the process sequence CoO. There is also a need for a low cost method of forming a contact structure for solar cells that have a low resistivity and clearly defined features.